In general, the thickness of a gate insulating layer of a transistor varies based on, among other things, the operating voltage of the transistor. Thus, in certain types of semiconductor devices, different regions of the semiconductor device may require gate insulating layers having different thicknesses based upon the type of transistors (e.g., low voltage or high voltage) included in that region of the device. Typically, non-volatile memory devices such as flash memories may require a high voltage in a write or erase operation. Accordingly, the gate insulating layers of the transistors used to implement non-volatile memory devices often typically be formed to have a thickness that is capable of resisting high voltages. In contrast, flash memory devices may be written or erased by tunneling charges that propagate through the cell gate insulating layers. Accordingly, the cell transistors used in flash memory applications may have thin gate insulating layers, which are often called tunnel insulating layers.
A method of fabricating a conventional semiconductor memory having multiple gate insulating layers is disclosed in Japanese Laid-Open Publication No. 2002-64157 entitled “SEMICONDCUTOR MEMORY INTEGRATION CIRCUIT AND METHOD OF FABRICATING THE SAME.” FIGS. 1–5 are cross-sectional views illustrating steps of fabricating a conventional semiconductor device having multiple gate insulating layers.
Referring to FIG. 1, a semiconductor substrate 10 is prepared. The semiconductor substrate includes a cell array region CELL, a high-voltage region HV and a low-voltage region LV. A tunnel insulating layer 21a and a first conductive layer 22a are formed on the cell array region CELL. A first gate insulating layer 21b and a second gate insulating layer 21c are formed on the high-voltage region HV and the low-voltage region LV, respectively. As tunnel insulating layers typically should provide high reliability as compared to other insulating layers, the tunnel insulating layer 21a and the first conductive layer 22a may be formed successively.
As shown in FIG. 2, a second conductive layer 22b, 22c may be formed on the first gate insulating layer 21b and on the second gate insulating layer 21c. Referring to FIG. 3, the first conductive layer 22a, the second conductive layer 22b, 22c, the first gate insulating layer 21b, the second gate insulating layer 21c and the substrate 10 may be patterned to form a trench. An insulating layer may be formed over the surface of the substrate. Chemical mechanical polishing may then be performed to form a device isolation layer 14 and to form a conductive pattern 22 from the conductive layers 22a, 22b, 22c. 
Referring to FIG. 4, a third conductive layer 24 is formed over the surface of the substrate. The third conductive layer 24 may then be patterned in the cell array region CELL. The third conductive layer 24 may be isolated by the device isolation layer 14 in the cell array region CELL.
As shown in FIG. 5, a dielectric layer 26 is formed over the surface of the cell array region CELL, and a fourth conductive layer 28 is formed on the dielectric layer 26 and on the third conductive layer 24.
In the above-described fabrication process, the tunnel insulating layer and the gate insulating layer may be formed before the device isolation layer is formed. Tunnel insulating layers may require high reliability. However, when the tunnel insulating layer is formed before the device isolation layer, physical stress may be applied to the tunnel insulating layer when the insulating layer is polished via chemical mechanical polishing. Likewise, stress may be applied to an edge of the tunnel insulating layer during the trench formation and filling processes as a result of etching damage and/or pressure.
Another method of fabricating a semiconductor device having multiple gate insulating layers is disclosed in U.S. Pat. No. 6,165,846 entitled “METHOD OF ELIMINATING GATE LEAKAGE IN NITROGEN ANNEALED OXIDES.” FIGS. 6–8 are cross-sectional views illustrating steps of fabricating another conventional semiconductor device having multiple gate insulating layers.
Referring to FIG. 6, a semiconductor device is prepared. The semiconductor device includes a cell array region CELL, a high-voltage region HV and a low-voltage region LV. A device isolation layer 90 is formed in the semiconductor substrate, and a buffer insulating layer 130 is formed on the surface of the substrate. A portion of the buffer insulating layer 130 is removed in the CELL region and a thin tunnel insulating layer 132 is provided.
Referring to FIGS. 7–8, a conductive pattern 140 is formed on the cell array region CELL, and a dielectric layer 180 is formed on the conductive pattern 140. Next, a first gate insulating layer 200′ and a second gate insulating layer 210 are formed at the high-voltage region HV and the low-voltage region LV, respectively. A conductive layer 220 is formed on the dielectric layer 180, the first gate insulating layer 200′ and the second gate insulating layer 210.
In the above-described fabrication process, the tunnel insulating layer may be formed after the device isolation layer is formed. As a result, the tunnel insulating layer may be protected from stress and/or damage caused by etching. However, after the device isolation layer is formed, insulating layers are formed and removed in the high-voltage region HV and the low-voltage region LV several times to form the first gate insulating layer and the second gate insulating layer. During the forming, removing and cleaning processes associated with the formation of these insulating layers, edges of the device isolation layer may be recessed to form a dent. As is well known in the art, such a dent may induce turn-on of a parasitic transistor resulting in a phenomena known as “hump phenomena.” Specifically, during the formation of the transistor, an active region may be formed having a low ion concentration to increase the breakdown voltage of a high-voltage transistor. When a well is formed by implanting boron, or in case of NMOS transistors for controlling threshold voltage, a parasitic transistor with low threshold voltage may be formed at the dent because the ion-concentration at the interface between the active region and the device isolation layer may be reduced by separation of the boron. As a result, the hump phenomenon may deepen.